Siemens KS7 Series Specifikace Strana 151

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Communications Mode CP 523
Example: Evaluating the status of the peripheral device
Start address 128 is set on the module.
If the peripheral device is not ready for operation, output 4.1 is set.
* 5.2
STL FB 118 Explanation
NAME :ERROR3
:L KH 0000
:T PW 128*
:L KH 0010
:L PY 129
:AW
:><F
:BEC
:S Q 4.1
:BE
Transfer nonrelevant data to the CP. The CP then updates the
transfer memory with the current data.
”Status of the peripheral device” evaluation
Set bits 0 to 3 to ”0”
Compare ACCUM 1 and ACCUM 2: If not equal,
Block End
Otherwise, set output 4.1
Block End
Example: Reading the current clock data
Start address 128 is set on the module.
The clock data is to be output to digital output modules beginning address 8.
* 5.2
STL FB 102 Explanation
NAME :CLOCKDAT
:L KH 0000
:T PW 128*
:L PY 129
:L KH 000F
:AW
:T QB 8
:L PW 130
:T QW 10
:L PW 132
:T QW 12
:L PW 134
:T QW 14
:BE
Load ACCUM 1 with nonrelevant data and transfer to the CP in
word 0 so that the CP will transfer the current data to the transfer
memory.
Read the current clock data and transfer to the digital output
modules.
When using the integral clock, you can evaluate the following additional flags in the status
byte:
Default time of day set (2X
H
)
This evaluation is only of use if you operate the programmable controller without a backup
battery.
Time of day or date error (3X
H
)
This error evaluation is only meaningful after you have set the clock.
Clock defective (1X
H
)
This error evaluation is only meaningful after a restart.
Note:
7-46
EWA 4NEB 811 6044-02a
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